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TCA62746AFG/AFNG
TOSHIBA CMOS Integrated Circuit Silicon Monolithic
TCA62746AFG,TCA62746AFNG
16-Output Constant Current LED Driver with Output Open/Short Detection
The TCA62746 series are LED drivers with sink type constant circuit output, making them ideal for controlling LED modules and displays. The current value of the 16-output is configurable using one external resistor. In addition, these drivers are equipped with a function for detecting the output voltage when the output load LEDs open or short, and which then outputs the result as serial data. These drivers consist of a 16-constant current output block, a 16-bit shift register, a 16-bit latch and a 16-bit AND-gate. The suffix (G) appended to the part number represents a Lead (Pb)-Free product.
TCA62746AFG
TCA62746AFNG
Features
* * 16-output built-in Output open detection (OOD) function : When in detection mode, outputs the detection results via SOUT. Output short detection (OSD) function : When in detection mode, outputs the detection results via SOUT. Output current setting range : 2 to 50 mA x 16-constant current output Current accuracy (@ REXT = 1.56 k, VO = 1.0 V, VDD = 5.0 V) : Between outputs: 1% (typ.) Between devices: 3% (typ.) Control data format: serial-in, parallel-out I/O logic: TTL level (Schmitt trigger input) Data transfer frequency: fMAX = 25 MHz (max) Power supply voltage: VDD = 4.5 to 5.5 V Operation temperature range: Topr = -40 to 85C Constant current output voltage: VO = 17V (max) Output delay circuit built-in: Internal data reset circuit for power-on resetting (POR) Backward compatible to TB62706B and TB62726A series drivers Package: FG type: SSOP24-P-300-1.00B FNG type: SSOP24-P-300-0.65A Weight SSOP24-P-300-1.00B : 0.32 g (typ.) SSOP24-P-300-0.65A : 0.14 g (typ.)
*
* *
* * * * * * * * *
Caution
This device is sensitive to electrostatic discharge. Please handle with care. The terminals which are marginal to electro static discharge are shown in the following table. (Please refer to page 22 for details.) ESD test MM Model Marginal terminals (MM Model Internal Standard 200V) 5,6,7,8,9,10,11,12,13,14,15,16,19,20 * ESD test HBM Model Internal Standard (2000V) is OK
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TCA62746AFG/AFNG
Pin Assignment (top view)
As shown below, this series has the same pin assignments as the TB62706B and TB62726A series:
GND SIN SCK
VDD REXT SOUT OE
SLAT
OUT0 OUT1
OUT2
OUT15 OUT14
OUT13
OUT3 OUT4
OUT5
OUT12 OUT11
OUT10
OUT6 OUT7
OUT9 OUT8
Note1: Short circuiting an output pin to a power supply pin (VDD or VLED*), or short-circuiting the REXT pin to the GND pin will likely exceed the rating, which in turn may result in smoldering and/or permanent damage. Please keep this in mind when determining the wiring layout for the power supply and GND pins. *VLED: LED power supply
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Block Diagram
OUT0 OUT1 OUT15
OSD
OSD OSD
3.0 V
OOD
0.3 V 16 OUT0 OUT1 Constant current outputs B.G POR OUT15 VDD
Delay1
Delay15
OOD
16
OOD
GND
OE
REXT
SLAT
OE OOD/OSD controller ST-OUT
G
Q15 Q0 Q1 16-bit D-latch D0 D1 D15
R
SIN SCK
D0
Q15 Q0 Q1 16-bit shift register ST D0~D15
Q15 R
SOUT
OSD S 16-bit MUX OOD
DO 16
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Truth Table
SCK SLAT H L H - *2 - *2 OE L L L L H SIN Dn Dn + 1 Dn + 2 Dn + 3 Dn + 3 Dn + 2 Dn + 2 OUT0 Dn OUT7 Dn - 7 OUT15 *1 Dn - 15 SOUT Dn - 15 Dn - 14 Dn - 13 Dn - 13 Dn - 13 Dn - 13 Dn - 13
No Change Dn - 5 Dn - 5 OFF
Note1: Note2:
When OUT0 to OUT15 output pins are set to "H" the respective output will be ON and when set to "L" the respective output will be OFF. "-" is irrelevant to the truth table.
Timing Chart
n=0 SCK L H SIN L H
SLAT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
H
L H
OE
L ON
OUT0
OFF ON
OUT1 OFF ON
OUT2
OFF
ON
OUT15
OFF H SOUT L
Note 1: Note 2:
The latch circuit is a leveled-latch circuit. Please exercise precaution as it is not triggered-latch circuit. Keep the SLAT pin is set to "L" to enable the latch circuit to hold data. In addition, when the SLAT pin is set to "H" the latch circuit does not hold data. The data will instead pass onto output. When the OE pin is set to "L" the OUT0 to OUT15 output pins will go ON and OFF in response to the data. In addition, when the OE pin is set to "H" all the output pins will be forced OFF regardless of the data.
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Pin Functions
Pin No 1 2 3 Pin Name GND SIN SCK I/O
Function The ground pin. The serial data input pin. The serial data transfer clock input pin. Also used for OOD/OSD mode settings. The latch signal input pin. Data is saved at L level. Also used for OOD/OSD mode settings. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. A sink type constant current output pin. The constant current output enable signal input pin. During the "H" level, the output will be forced off. Also used for OOD/OSD mode settings. The serial data output pin. This pin outputs the OD/OSD detection result data. The constant current value setting resistor connection pin. The power supply input pin.
I I
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
SLAT
I O O O O O O O O O O O O O O O O I
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OE
22 23 24
SOUT REXT VDD
O

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Absolute Maximum Ratings (Ta = 25C)
Characteristics Power supply voltage Output Logic current voltage Symbol VDD IO VIN VO Topr Tstg Rth(j-a) PD Rating *1
-0.4 to 6.0
Unit V mA V V C C C/W W
55
-0.3 to VDD + 0.3 *2 -0.3 to 17 -40 to 85 -55 to 150
input
Output
voltage
Operating temperature Storage Thermal Power temperature resistance dissipation
94(AFG type When mounted PCB)/120(AFNG type When mounted PCB) *3 1.32(AFG type When mounted PCB)/1.04(AFNG type When mounted PCB) *3,4
Note1: Voltage is ground referenced. Note2: However, do not exceed 6V. Note3: PCB condition 76.2 x 114.3 x 1.6 mm, Cu 30% (SEMI conforming) Note4: The power dissipation decreases the reciprocal of the saturated thermal resistance (1/ Rth(j-a)) for each degree (1C) that the ambient temperature is exceeded (Ta = 25C).
Recommended Operating Conditions
DC Items (Unless otherwise specified, Ta = -40C to 85C)
Characteristics Power supply voltage O u t p u t v o l ta ge wh e n O F F Output voltage when ON High level logic input voltage Low level logic input voltage High level SOUT output current Low level SOUT output current Constant current output Symbol VDD VO (OFF) VO (ON) VIH VIL IOH IOL IO VDD = 5 V VDD = 5 V OUTn OUTn Test Conditions
Min 4.5
Typ.

Max 5.5 16 4 VDD 0.8
-1
Unit V V V V V mA mA mA
OUTn

0.7 2.0 GND

1 50
2
AC Items (Unless otherwise specified, VDD = 4.5 to 5.5 V, Ta = -40C to 85C)
Characteristics Serial data transfer frequency Clock Latch Enable pulse pulse pulse width width width Symbol fSCK twSCK twSLAT twOE1 twOE2 tHOLD1 H o l d t i m e tHOLD2 tHOLD3 tHOLD4 tSETUP1 S e t u p t i m e tSETUP2 tSETUP3 tSETUP4 Maximum clock rise time Maximum clock fall time tr tf Test Circuits 7 7 7 7
Test Conditions
Min
Typ.

Max 25

Unit MHz ns ns ns
s
SCK = "H" or "L"
20 20 100 2 5 5 10 10 5 5 10 10

SLAT = "H"
OE = "H" or "L" ,REXT = 500 When error is detected *1

7 7 7 7 7 7 7 7 7 7 *2 *2
ns ns ns ns ns ns ns ns ns ns
500 500
Note1: Please refer to page 16 for details of the error detection. Note2: If the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock waveform, it may not be possible to achieve the timing required for data transfer. Please keep these timing conditions in mind when designing your application.
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Electrical Characteristics (Unless otherwise specified, VDD = 4.5 to 5.5 V and Ta = 25C)
Characteristics High level logic output voltage Low level logic output voltage High level logic input current Low level logic input current Symbol VOH VOL IIH IIL IDD1 IDD2 IDD3 IDD4 IDD5 IO1 Constant current output IO2 Output OFF leak current Constant current error Constant current power supply voltage regulation Constant current output voltage regulation Pull-up Pull-down resistor resistor IOK
IO
Test Circuits 1 1 2 3 4 4
Test Conditions IOH = -1 mA, SOUT IOH = +1 mA, SOUT VIN = VDD, OE , SIN, SCK VIN = GND, SLAT , SIN, SCK VO = 16 V, No REXT SCK = "L", OE = "H" REXT = 1.56 k, All output OFF REXT = 500 , All output OFF REXT = 1.2 k, All output ON REXT = 500 , All output ON VDD = 5.0V, VO = 1.0 V, REXT = 1.56 k VDD = 5.0V, VO = 1.0 V, REXT = 500 VO = 16 V, REXT = 1.56 k, All output OFF VDD = 5.0V, VO = 1.0 V, REXT = 1.56 k, OUT0 to OUT15 VDD = 4.5 to 5.5V, VO = 1.0 V, REXT = 1.56 k, OUT0 to OUT15 VDD = 5.0V, VO = 1.0 to 3.0 V, REXT =1.56 k, OUT0 to OUT15 OE
Min VDD - 0.4

Typ.

Max
Unit V V
A A
0.4 1
-1
0.1

0.5 7.0
mA mA
Power supply current
4
14.0
mA
4
7.0
mA
4
14.0
mA
5
14.1
15
15.9
mA
5
44.2

47
1 1 1
49.8
mA
A
5 5 5 5 3 2
0.5
3 4 4
% %/V %/V k k
%VDD %VO RUP RDOWN
250 250
500 500
800 800
SLAT
Electrical Characteristics during OOD/OSD Mode (Unless otherwise specified, VDD = 4.5 to 5.5 V and Ta = 25C)
Characteristics OOD OSD voltage voltage Symbol VOOD VOSD Test Circuits 6 6 Test Conditions REXT = 464 ~11.5 k REXT = 464 ~11.5 k Min
Typ. 0.30 3.0
Max 0.40
Unit V V
2.85
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Switching Characteristics (Unless otherwise specified, Ta = 25C and VDD = 5.0 V)
Characteristics SCK- OUT0 SLAT - OUT0 Symbol tpLH1 tpLH2 tpLH3 tpLH tpHL1 tpHL2 tpHL3 tpHL tor tof Test Circuits 7 7 7 7 7 7 7 7 7 7 7 7 Test Conditions Min

Typ. 20 20 20 10 50 50 50 20 30 70 20
20
Max 100 100 100
Unit
SLAT = "H", OE = "L"
OE = "L"
OE - OUT0
Pr o pa ga ti o n delay time SCK-SOUT SCK- OUT0 SLAT - OUT0
SLAT = "H"
5

ns
SLAT = "H", OE = "L"
OE = "L"
100 100 100
OE - OUT0
SCK-SOUT Output Output Output Output rise fall delay delay time time
SLAT = "H"
15

10 to 90% of voltage waveform 90 to 10% of voltage waveform
150 150
ns ns ns
ns
t i m e tDLY (ON) t i m e tDLY (OFF)
OUTn - OUT(n + 1) between adjacent outputs
OUTn - OUT(n + 1)
between adjacent outputs
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I/O Equivalent Circuits
1. SCK, SIN
VDD (SCK) (SIN) GND
2. OE
VDD
OE
GND
3. SLAT
VDD
4. SOUT
VDD SOUT GND
SLAT
GND
5. OUT0 to OUT15
OUT0 to OUT15
GND
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Test Circuits
Test Circuit1: High level logic input voltage / Low level logic input voltage
SCK F.G SIN
SLAT
VDD
OUT0
OE
OUT7
OUT15 VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%) REXT GND SOUT
VDD = 4.5~5.5 V VDD = 4.5~5.5 V VDD = 4.5~5.5 V
REXT
IO = -1mA~1mA
CL = 10.5 pF
V
Test Circuit2: High level logic input current / Pull-down resistor
VIN = VDD
A A A
SCK SIN
SLAT
VDD
OUT0
A
OE
OUT7
OUT15
REXT GND SOUT
CL = 10.5 pF
Test Circuit3: Low level logic input current / Pull-up resistor A A A A
SCK SIN
SLAT
REXT
VDD
OUT0
OE
OUT7
OUT15
REXT GND SOUT
CL = 10.5 pF
REXT
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Test Circuit4: Power supply current
SCK F.G SIN
SLAT
VDD
OUT0
OE
OUT7
OUT15 VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%)
A
REXT
REXT = 1.56k, 500
GND
SOUT
VDD = 4.5~5.5V CL = 10.5 pF
Test Circuit5: Constant current output / Output OFF leak current / Constant current error Test Circuit5: Constant current power supply voltage regulation / Constant current output voltage regulation
SCK F.G SIN
SLAT
VDD
OUT0
A
OE
OUT7
A
OUT15 VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%) REXT
REXT = 1.56k, 500
A
GND
SOUT
CL = 10.5 pF
VO = 1V, 3V, 16V
Test Circuit6: OOD voltage / OSD voltage
SCK F.G SIN
SLAT
VDD
OUT0
V
OUT7
OE
V
OUT15
VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%)
V
REXT
REXT = 464 , 11.5k
GND
SOUT
CL = 10.5 pF VDD = 4.5 V~5.5 V
VO1 = 1 V
VDD = 4.5~5.5V
All output terminals is set to turning on, only one output terminal is connected with the VO2 power supply, and VO2 is changed. VOOD/VOSD is confirmed by the error detection result from SOUT.
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VO2
TCA62746AFG/AFNG
Test Circuit7: Switching Characteristics
SCK F.G SIN
SLAT
VDD
RL = 85 OUT0 CL OUT7 RL CL
OE
OUT15
VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%) REXT
REXT = 500
RL
GND
SOUT
CL = 10.5 pF
CL = 10.5 pF
VDD = 4.5~5.5 V
Output Delay Circuit
This is designed for high speed switching between outputs and is intended to have the effect of reducing switching noise by reducing the di/dt when all outputs are ON or OFF at the same time.There is a switching time lag (20 ns typ.) between adjacent outputs. The equivalent circuit chart of the delay circuit is shown in the following.
OE
OUT0
D0 x1
OUT1
D1 Delay
x2
OUT2
D2 Delay Delay
x15
VLED =5V
OUT15
D15 Delay Delay
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Timing Waveforms
1. SCK, SIN, SOUT
twSCK SCK 50% tSETUP1 SIN 50% tHOLD1 SOUT 50% tpLH/tpHL 50% 50% twSCK 50% 90% 10% tr tf 90% 10%
2. SCK, SIN, SLAT , OE , OUT0
SCK
50%
50%
SIN tHOLD2 SLAT 50% twSLAT
OE
tSETUP2 50% twOE1 50% 50%
OUT0 tpHL1/tpLH1 tpHL2/tpLH2
50%
3. OUT0
twOE1 50% OE
50%
tpHL3
tpLH3
OFF 90% OUT0 10% tof 10% tor ON 50% 50% 90%
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4. OOD Mode/OSD Mode
twsck SCK 50% tSETUP3 tHOLD3
OE
50%
50%
50%
50% tSETUP4 tHOLD4
SLAT
50%
50%
5. OOD/OSD Read Mode
SCK
50%
50%
OE
50%
50%
twOE2
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PWM grayscale control
This IC is possible to PWM grayscale control by the input of the PWM signal to the EN terminal. When PWM grayscale control is done, we recommend the LED power-supply voltage to be set to become the satiety region of the constant current characteristic. When using this IC outside the saturation area, PWM grayscale control cannot be normally done.
Switching to Open Circuit Detection (OOD) and Short Circuit Detection (OSD) Modes
Switching to OSD mode
1 SCK 2 3 4 5 6
OE SLAT
H L
L L
H L
H H
H L
H L
The signal sequence set to be in the OSD mode. Here, the SLAT active pulse would not latch any data.
Switching to OOD mode
1 SCK OE SLAT H L
2
3
4
5
6
L L
H L
H L
H L
H H
The signal sequence set to be in the OOD mode. Here, the SLAT active pulse would not latch any data.
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Reading Error Status Code
n>3 = 1 SCK MIN 2 s 2 3
OE
SOUT
H
L
L
L
H
H
H
H
H
Bit 15
Error status code Bit Bit Bit Bit Bit 14 13 12 11 10
When the above signal sequence is set in the OOD and OSD modes, the error state code can be read through the terminal SOUT. Error state code of OOD detection mode Error state code VOOD VO VOOD < VO Error state code of OSD detection mode Error state code VOSD VO VOSD > VO 0 1 State of output terminal Short circuit Normal 0 1 State of output terminal Open circuit Normal
Description
In the OOD and OSD modes, the state of OE must be switched from "H" to "L". And, then, This IC would execute Open-/Short-circuit Detection as well as enabling output ports to drive current. At least three clock must be inputs at the "L" state of OE and the third clock should be at least 2 s after the falling edge of OE . the detected error status into the built-in shift register is done by rising edge of this third clock. When OE is "L", the serial data cannot be input from the terminal SIN. When OE is changed from "L" to "H", the error state code is output from the terminal SOUT synchronizing with the clock.
Switching to Normal Mode
1 SCK OE SLAT H L L L H L H L H L H L "L" level 2 3 4 5 6
The signal sequence set to be in the Normal mode.
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Timing chart of error detection mode (OSD mode)
SOUT, 0 SIN, 0 SCK
SLAT OE
SIN, 1 SOUT, 1 TCA62746, 1
SIN, 2 TCA62746, 2
SOUT, 2 TCA62746, N-2 TCA62746, N-1
SOUT, N-1
TCA62746, 0
1 SCK
2
3
4
5
6
N x 16 CLK
3 CLK or more
N x 15 CLK
1
2
3
4
5
6
SIN N x 16-1
SLAT
SIN, 0
2
1
0 2CLK 2 s
Don't care
OE
SOUT, 0 SOUT, 1
15 31
14 30
SOUT, N-1 A. Switching to Error detection mode B. Setting of output terminal that does the error
N x16-1
C. Detection the error
D. Reading back the error status code Error: 0, Normal: 1
E. Switching to Normal
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Reference data
*This data is provided for reference only. Thorough evaluation and testing should be implemented when designing your application's mass production design.
Set output current - Duty cycle graph
IO - Duty
60 60
IO - Duty
50
50
40 IO (mA) IO (mA)
40
30
30
20
20
10
VDD=5.5V VO=1.0V Ta=25C ON PCB
All output ON
0 20 40 60
TCA62746AFG TCA62746FG TCA62746AFNG TCA62746FNG
10
VDD=5.5V VO=1.0V Ta=55C ON PCB
All output ON
0 20 40 60
TCA62746AFG TCA62746FG TCA62746AFNG TCA62746FNG
0 80 100 Duty - Turn on rate (%)
0 80 100 Duty - Turn on rate (%)
IO - Duty
60
P D - Ta
1.4 TCA62746FG TCA62746AFG 1.2
50
TCA62746AFNG TCA62746FNG
1.0
40 IO (mA)
30
P D (W)
0.8
0.6
20
10
VDD=5.5V VO=1.0V Ta=80C ON PCB
All output ON
0 20 40 60
0.4
TCA62746FG TCA62746AFG TCA62746FNG TCA62746AFNG
0.2
ON PCB
0.0
100
0 80 Duty - Turn on rate (%)
0
10
20
30
40 Ta (
50 )
60
70
80
90
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Reference data
*This data is provided for reference only. Thorough evaluation and testing should be implemented when designing your application's mass production design.
Output Current - REXT Resistor
50 45 40 35 IO (mA) 30 25 20 15 10 5 0 0 1 2 3 4
VDD=5.0V VO=1.0V Ta=25C
IO - REXT
Theoretical value
IO (A) = (1.23(V) / REXT ()) x 19
567 REXT (k )
8
9
10 11 12
Constant current characteristic
IO - VO 60
VDD=5.0V VO=1.0V Ta=25C
50 40 IO (mA)
30
20 10
0 0.0 0.5 1.0 1.5 VO (V) 2.0 2.5 3.0
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Package Dimensions
Weight: 0.32 g (typ.)
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Package Dimensions
Weight: 0.14 g (typ.)
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Serge resisting
The terminals which are weak to electro static discharge are shown in the following table. MM Model ESD test Result (Internal Standard 200V) - Serge Standard VDD VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND GND TEST Result 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V Standard VDD VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND GND + Serge TEST Result 200V 200V 200V 200V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 200V 200V 200V 200V
pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
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Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Application Circuits
The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits.
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment.
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IC Usage Considerations
Notes on handling of ICs
[1] The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. [2] Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. [3] If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. [4] Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. [5] Carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. If there is a large amount of leakage current such as input or negative feedback condenser, the IC output DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC that inputs output DC voltage to a speaker directly.
24
2007-05-22
TCA62746AFG/AFNG
25
2007-05-22

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